The present invention relates to digital delay devices, and more particularly to an active selectable digital delay circuit that merges digital gates with a multiplexer.
Previous active selectable digital delay devices, such as that shown in U.S. Pat. No. 4,646,297 issued Feb. 24, 1987 to Steven R. Palmquist et al entitled "Skew Detector", especially FIG. 7, have used a plurality of delay elements connected in series with the output of each delay element being input to a multiplexer. Each delay element has a fixed delay time, and by selecting which delay element is output by the multiplexer a total delay of n*dt is achieved, where n is the number of delay elements in the series of delay elements selected by the multiplexer and dt is the delay time for each delay element. Since each delay element requires its own current source and the delay range is a function of the total number of delay elements, this requires a large number of devices with a corresponding relatively high power requirement.
What is desired is an active selectable digital delay circuit that merges the digital gates with the multiplexer to reduce power consumption, area and minimum delay.